View STEL-2030C_197526.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STEL-2030C Data Sheet
STEL-2030C
17 Mbps Convolutional Encoder Viterbi Decoder
R
FEATURES
n n n 17 Mbps MAX. OPERATING DATA RATE CONSTRAINT LENGTH K = 7 G1 = 1718, G2 = 1338 MULTIPLE DEVICES CAN BE MULTIPLEXED TO GIVE HIGHER DATA RATES OPTIMIZED INTERFACE TO OPERATE WITH BPSK, QPSK, AND OQPSK DEMODULATORS V.35 SCRAMBLER AND DESCRAMBLER WITH CCITT AND IESS OPTIONS DIFFERENTIAL ENCODER AND DECODER AUTO NODE SYNC CAPABILITY INTERNAL BER MONITOR MULTIPLE RATES: R = 1/2, 2/3*, 3/4* (* Punctured codes) n n n INTERNAL PUNCTURING CAPABILITY 5.2 dB CODING GAIN @10-5 BER 84-PIN PLCC PACKAGE
FUNCTIONAL DESCRIPTION
Convolutional Encoding and Viterbi Decoding are used to provide forward error correction (FEC) which improves digital communication performance over a noisy link. In satellite communication systems where transmitter power is limited, FEC techniques can reduce the required transmission power. The STEL-2030C is a specialized product designed to perform this specific communications related function. It is functionally identical to the previously available STEL2030B, which it replaces. The encoder creates a stream of symbols which are transmitted at twice the information rate. This encoding introduces a high degree of redundancy which enables accurate decoding of the information despite a high symbol error rate resulting from a noisy communications link.
n
n n n n n
BLOCK DIAGRAM
ECLKOUT
ECLKIN ERESET EDAT V.35 SCRAMBLER 7-BIT SHIFT REGISTER Q1 Q2 Q3 Q4 Q5 Q6 Q7
ESEL ESCRAM EDIF OBIN OQPSK PARL LDG2 G1 2-0 G2 2-0 PNCG1/G2 CLKSEL DCLKIN SYNC DRESET TBD COUNT THR DDIF DSEL DSCRAM
8 8
EG1 (1718)
EG2 (1338) BERR G1ERR G2ERR AUTO OOS
BER MONITOR
3 3 2
SYMBOL ALIGNMENT CIRCUIT
METRIC ASSIGNMENT
VITERBI DECODER (ACS)
TRACEBACK MEMORY TIMING AND CONTROL DIFFERENTIAL DECODER V.35 DESCRAMBLER ODCLK
DATO
STEL-2030C
2
The STEL-2030C contains a K = 7 convolutional encoder and Viterbi decoder (including differential, as well as direct encoding/decoding) capable of fully independent (full duplex) operation, with completely independent data clocks. At the decoder the symbol input format can be either serial, i.e., sequential symbols, (typically for BPSK applications) or parallel (typically for QPSK and OQPSK applications).
The data inputs can be in offset binary or offset signed magnitude formats, with 3-bit soft decision. Auto node sync and a BER monitor are also provided in the device. Rate 2/ 3 3 and /4 punctured signals can be encoded and decoded, as well as non-punctured, Rate 1/2, signals. The polynomials used are industry standards.
PIN CONFIGURATION
Package: 84-pin PLCC Thermal coefficient, qja = 30 C/W
11 8888877777 109876543214321098765
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Top View
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
0.017" 0.004" (2)
1.190" 0.005"
0.05" nominal (1)
333333344444444445555 345678901234567890123
1.154" 0.004"
0.200" max.
Notes: (1) Tolerances on pin spacing are not cumulative (2) Dimensions at seating plane PIN CONNECTIONS 18 1 VDD 19 2 VSS 20 3 THR0 21 4 THR1 22 5 THR2 23 6 THR3 24 7 THR4 25 8 VSS 26 9 THR5 27 10 THR6 28 11 THR7 29 12 ECLKIN 30 13 EDIF 31 14 ESCRAM 32 15 ESEL 33 16 VSS 34 17 ERESET EDAT VDD DRESET DCLKIN VSS PNCG2 G20 G21 G22 PNCG1 VSS G10 G11 G12 LDG2 SYNC OBIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 PARL OQPSK VSS DSCRAM DSEL DDIF TBD VSS N.C. VDD CLKSEL VDD VDD N.C. N.C. VDD VSS 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 N.C. VSS I.C. N.C. N.C. VSS VDD OOS AUTO N.C. N.C. VSS BERR VDD G2ERR G1ERR ODCLK 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DATO VDD VSS EG2 EG1 ECLKOUT VSS COUNT0 COUNT1 COUNT2 COUNT3 VSS COUNT4 COUNT5 COUNT6 COUNT7
Notes: I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias. N.C. denotes No Connection. These pins can be used for vias.
3
STEL-2030C
ENCODER OPERATION
The convolutional coder is functionally independent from the decoder. A single data bit is clocked into the 7-bit shift register on the rising edge of ECLKIN. Two symbols, G1 and G2, are generated and are brought out on separate pins, EG1 and EG2.
INPUT SIGNALS
ERESET Encoder Reset. A logic low on this asynchronous input will completely reset all internal registers in the encoder to an initial condition within 100 nanoseconds. This sets the encoder state to all zeroes. ECLKIN The transmit clock is the encoder system clock. The maximum ECLKIN frequency is 17 MHz. There is no minimum frequency. Data is latched into the encoder on the falling edges of this clock. EDAT The encoder input data is connected to this input. The data is clocked in on the falling edge of the ECLKIN signal. EDIF When the EDIF signal is set high it enables the differential encoder circuit. When it is set low this circuit will be disabled, and normal, non-differential data will be loaded into the convolutional encoder. ESCRAM When this input is set high it causes the encoded data to be scrambled before being differentially encoded and before being convolutionally encoded. The scrambling algorithm used is the standard CCITT or IESS V.35 algorithms according to the setting of ESEL.. When ESCRAM is set low the scrambler function will be inhibited. ESEL When this input is set low the CCITT compatible mode is selected for the V.35 scrambler in the encoder, and when it is set high the IESS compatible mode is selected. DRESET Decoder Reset. A logic low on this asynchronous input will completely reset all registers in the decoder to an initial condition within 3 clock cycles. This will not affect the values stored in the decision path memory. DCLKIN Decoder clock input. It is the reference clock for all internal synchronous functions in the decoder. It should nominally be a square wave. When CLKSEL is set low the DCLKIN signal should be at twice the frequency of the input symbols, with a maximum frequency of 68 MHz when PARL = 0 and 34 MHz when PARL = 1, corresponding to a decoded data rate of 17 Mbps. When CLKSEL is set high the DCLKIN signal should be at the same frequency as the input symbols, with a maximum frequency of 20 MHz when PARL = 0 and 10 MHz when PARL = 1, corresponding to a decoded data rate of 10 Mbps. 4
DECODER OPERATION
The decoder section of the STEL-2030C implements the Viterbi algorithm for decoding convolutionally encoded data. It incorporates many unique features which enhance its capabilities and flexibility. The incoming symbols can be accepted either sequentially, as would be the case in a BPSK system, or in parallel, as would be the case in a QPSK system. In addition, a special circuit takes care of symbol alignment in an Offset QPSK (OQPSK) system. The signals can be in either offset binary or signed magnitude codes. In both cases the codes are offset from zero by half a quantization level, giving the same number of allowable states in both the positive and negative directions. The Viterbi decoder itself uses the add/compare/select algorithm to determine the most likely value for each bit from the trellis created from the received symbols. Five-bit arithmetic is used to maximize the performance with the three-bit soft-decision data inputs. The decoder contains many user controlled features which enhance its performance in different environments. The depth of the trace-back used can be set to the long mode (70 states) for optimum performance in the punctured modes (R = 2/3, 3/4, 7/8), or to the short mode (38 states) in normal mode (R = 1/2). (The penalty for using the longer trace-back length is the additional delay in decoding the data.) A built-in counter estimates the probability of incorrect node synchronization from the error rate. A user selectable feedback loop allows the node synchronization to be corrected automatically, and the device also features a built-in bit error-rate (BER) monitor circuit as well as a V.35 descrambler. The true CCITT V.35 algorithm is supported as well as the IESS version of this algorithm.
STEL-2030C
G12-0, G22-0 The G12-0 and G22-0 signals are the 3-bit soft decision input symbols to the decoder. They are presented to the decoder either sequentially or in parallel depending on the state of the PARL signal. In the parallel mode (PARL = 1) the symbols are clocked into the device on the falling edge of DCLKIN (alternate edges only when CLKSEL = 0). In the sequential mode (PARL= 0) the G22-0 inputs are not used, both the G1 and G2 symbols are loaded via the G12-0 pins. The G1 symbols are then latched in on the falling edges of DCLKIN when LDG2 is low and the G2 symbols are latched in on the falling edges of DCLKIN when LDG2 is high. OBIN The STEL-2030C can accept the soft-decision input data in either offset binary or signed magnitude formats. When the OBIN signal is set high the format expected will be offset binary, and when it is set low it will be signed magnitude. The meanings of the 3-bit values for these two codes is shown in the table. OBIN = 1 111 110 101 100 011 010 001 000 OBIN = 0 111 110 101 100 000 001 010 011 Value Most confident + (Data = 1) Least confident + Least confident (Data = 0) Most confident
OQPSK When this signal is high the device is set up to operate with Offset QPSK (OQPSK) data. This is only valid when PARL is also set high. DDIF When this input is set high it causes the data out of the Viterbi decoder to be differentially decoded. This function precedes the descrambler. DSCRAM When this input is set high it causes the data out of the Viterbi decoder to be descrambled. The descrambling algorithm used is the CCITT or IESS V.35 algorithms according to the setting of DSEL, and descrambling follows differential decoding when this is enabled. When the DSCRAM signal is set low, this function will be inhibited. DSEL When this input is set low the CCITT compatible mode is selected for the V.35 descrambler in the decoder is set into and when it is set high the IESS compatible mode is selected. PNCG1, PNCG2 The PNCG1 and PNCG2 signals are used to control the STEL-2030C when operating in punctured mode. In normal (Rate = 1/2) operation these pins should be set low. In punctured mode the PNCG1 signal must be set high to indicate that the G1 symbol is punctured and the PNCG2 signal must be set high to indicate that the G2 symbol is punctured. A symbol will be punctured when the PNCG1 or PNCG2 signals are high during the falling edge of DCLKIN which latches the corresponding symbol in to the decoder. Zero value metrics will be substituted internally for the actual metrics corresponding to the signals present on the G12-0 or G22-0 pins at that time. TBD This signal selects the Trace-Back Depth used in the decoding process. When it is set low the traceback depth will be 70 states, and when it is set high the traceback depth will be 38 states. The longer traceback depth gives better performance, especially in the punctured modes; the shorter traceback depth gives a shorter latency. SYNC When the SYNC input is set high during the rising edge of DCLKIN the internal symbol synchronization will be changed. When auto node sync is not desired this pin should be set low. It should be connected to the AUTO output to use the auto node sync capability of the STEL-2030C. The state of this circuit will always be set to normal after a reset.
When using the STEL-2030C with hard-decision data the symbols should be loaded into the G12 and G22 pins. The other symbol inputs should be set to a logic high level and OBIN should be set low. LDG2 When this signal is high during a rising edge of DCLKIN the symbol loaded into the G12-0 pins on the next falling edge of DCLKIN will be G2. This function is only active when PARL is set low (sequential input mode). PARL When this signal is high the input symbols are accepted in parallel by the chip, using the G12-0 pins for the G1 symbols and the G22-0 pins for the G2 symbols. When it is set low the inputs are accepted sequentially, using the G12-0 pins for both symbols. The sequential input is most suited for BPSK data and the parallel input is most suited for QPSK data.
5
STEL-2030C
COUNT7-0 This 8-bit input signal defines the period (number of bits) used in the node synchronization circuit. The 8-bit number N is used to set up a period of (256N+256) internally, where N is the value of COUNT7-0. If the renormalization count exceeds the threshold value during a period of this number of bits then an out-of-sync condition is declared (i.e., the output pin OOS is switched to High and AUTO is toggled). THR7-0 This 8-bit input signal defines the threshold for node synchronization. The 8-bit number N is used to set up a threshold value of (8N+2) internally, where N is the value of THR7-0. If the renormalization count is greater than this threshold value then an out-of-sync condition is declared (i.e., the output pin OOS is switched to High and AUTO is toggled). CLKSEL When Clock Select is set low the STEL-2030C operates in its normal mode with DCLKIN running at twice the input symbol rate. When it is set high the device operates in the alternative mode with DCLKIN running at the same rate as the input symbols. This allows the device to be used in circuits having this clock requirement.
of the clock the data will always be valid on the rising edge of the divider output. OOS This output pin serves as a flag for the out-of-sync condition. When it goes high it signifies that the renormalization count in the internal node sync circuit has exceeded the threshold value set by the THR7-0 signal and the out-of-sync condition is declared. It will remain high until this condition ceases to exist. i.e., the next time the threshold is not exceeded during a complete count period. AUTO This is the feedback signal from the internal node sync correction circuit. It will pulse high for one cycle of DCLKIN each time the renormalization count in the internal node sync circuit has exceeded the threshold value set by the THR7-0 signal and the out-of-sync condition is declared. It should be connected to the SYNC input when using the internal node sync facility. BERR The Bit Error output indicates that an error has been detected in either the G1 or G2 symbols corresponding to the current output bit. Note that when operating with punctured codes (Rates 2/3 and 3/4) the BERR output will pulse once for each symbol during which either PNCG1 or PNCG2 is set high. There will be a delay corresponding to the throughput delay of the decoder and encoder circuits between each instance of PNCG2 or PNCG2 being set high and the corresponding pulse on BERR. G1ERR The G1 Error output indicates that an error has been detected in the G1 symbol corresponding to the current output bit. Note that when operating with punctured codes (Rates 2/3 and 3/4) the G1ERR output will pulse once for each symbol during which PNCG1 is set high. There will be a delay corresponding to the throughput delay of the decoder and encoder circuits between each instance of PNCG1 being set high and the corresponding pulse on G1ERR. G2ERR The G2 Error output indicates that an error has been detected in the G2 symbol corresponding to the current output bit. Note that when operating with punctured codes (Rates 2/3 and 3/4) the G2ERR output will pulse once for each symbol during which PNCG2 is set high. There will be a delay corresponding to the throughput delay of the decoder and encoder circuits between each instance of PNCG2 being set high and the corresponding pulse on G2ERR. 6
OUTPUT SIGNALS
EG1, EG2 The EG1 and EG2 signals are the two encoded sym-bols generated with the polynomials G1 = 1718 and G2 = 1338. ECLKOUT This signal is a replica of the ECLKIN signal. The output signals G1 and G2 change on the rising edges of this clock. DATO Decoded data output. This is the output of the Viterbi decoder. The output data bits are delayed by 163 clock cycles relative to the corresponding input symbols, G12-0 and G22-0 when operating in the short trace-back depth mode (TBD = 1), and 291 clock cycles when operating in the long trace-back depth mode (TBD = 0). This signal changes on the rising edges of ODCLK. ODCLK Output data clock. All outputs change on the rising edge of this clock. The falling edge of ODCLK can be used as a strobe for DATO output, which is guaranteed to be valid on this edge. Note that when CLKSEL = 0 and PARL = 1 the frequency of ODCLK is twice that of the data. If this clock is divided by 2 with a divider triggering on the falling edge
STEL-2030C
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning:
Symbol
Ts Ta VDDmax VI/O(max) VI/O(min)
Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods may also affect device reliability. Parameter
Storage Temperature Operating Temperature Max. voltage between VDD and VSS Max. voltage on any input or output pin Min. voltage on any input or output pin
{ {
Range
-40 to +125 -55 to +125 -40 to +85 -55 to +125
Units
C C C C volts volts volts (Plastic package) (Ceramic package) (Plastic package) (Ceramic package)
+7 to -0.7 VDD + 0.3 VSS - 0.3
RECOMMENDED OPERATING CONDITIONS Symbol
VDD Ta Supply Voltage Operating Temperature (Ambient)
Parameter
Range
volts C (Plastic package) C
Units
{
+5 5% 0 to +70 -55 to +125
(Ceramic package)
D.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 5% volts, Ta = 0 to 70 C) Symbol
IDD(Q) IDD IDD VIH(min) VIL(max) VOH(min) VOL(max) IIH(max) IIL(max)
Parameter
Supply Current, Quiescent Supply Current, Operational Supply Current, Operational Min. High Level Input Voltage Max. Low Level Input Voltage Min. High Level Output Voltage Max. Low Level Output Voltage Max. High Level Input Current Max. Low Level Input Current
Min.
Typ.
2 8
Max.
1.0
Units
mA mA/Mbps mA/Mbps volts
Conditions
Static, no clock CLKSEL = 0, PARL = 0 All other modes Guaranteed Logic '1' Guaranteed Logic '0' IO = -4.0 mA IO = +4.0 mA VIN = +5.0 volts VIN = 0 volts
2.0 0.8 2.4 0.4 10 -10
volts volts volts A A
7
STEL-2030C
ENCODER TIMING
E C L K IN
tD S tD H
E D AT
BIT 1
X
BIT 2
X t EC C
BIT 3
X
B IT 4
X
E C LK O UT t ECD
EG 1, EG 2
ENCODER A.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 5% volts, Ta = 0 to 70 C)
Symbol tDS tDH tECC tECD fECLK Parameter EDAT to ECLKIN setup EDAT to ECLKIN hold ECLKIN to ECLKOUT stable delay ECLKOUT to G1 G2 stable delay ECLKIN frequency Min. 10 5 30 5 17 Max. Units nsec. nsec. nsec. nsec. MHz Conditions
DECODER A.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 5% volts, Ta = 0 to 70 C)
Symbol fDAT tSU tHD tCD tOD Parameter Data speed G1, G2, PNCG1 or PCNG2 to DCLKIN Setup G1, G2, PNCG1 or PCNG2 to DCLKIN Hold DCLKIN to ODCLK stable delay ODCLK to any other output stable delay 10 5 20 12 Min. Max. 17 Units Mbps nsecs. nsecs. nsecs. nsecs. Conditions
STEL-2030C
8
DECODER TIMING (a) PARALLEL INPUT MODE (PARL = 1)
1. CLKSEL = 1
DCLKIN
t SU G1/G2 SYMB. N-1 SYMB. N SYMB. N+1 SYMB. N+2
t HD SYMB. N+3 SYMB. N+4 SYMB. N+5
PNCG1/G2 t CD
ODCLK t OD
DATO
BIT 0
BIT 1
BIT 2
BIT 2
BIT 3
BIT 4
2. CLKSEL = 0
DCLKIN t SU t HD G1/G2 SYMB. N-1 SYMB. N SYMB. N+1 SYMB. N+2 SYMB. N+3 SYMB. N+4 SYMB. N+5
PNCG1/G2 t CD
ODCLK t OD
DATO
BIT 0
BIT 1
BIT 2
BIT 2
BIT 3
BIT 4
Notes: 1. 2.
N = 163 when TBD = 1, N = 291 when TBD = 0 When CLKSEL = 1 an internal double speed clock is generated whose rising edges are generated on the edges of DCLKIN.
9
STEL-2030C
DECODER TIMING (b) SEQUENTIAL INPUT MODE (PARL = 0)
1. CLKSEL = 1
DCLKIN
t SU LDG2 t SU G1/2 G1 G2 G1 G2 G1
t HD
t HD G2 G1 G2
PNCG1/G2 t CD
ODCLK t OD
DATO
2. CLKSEL = 0
DCLKIN t SU t HD LDG2 t SU G1/2 G2 G1 G2 G1 G2 t HD G1 G2 G1
PNCG1/G2 t CD
ODCLK t OD
DATO
Note: When CLKSEL = 1 an internal double speed clock is generated whose rising edges are generated on the edges of DCLKIN.
STEL-2030C
10
DECODER A.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 5% volts, Ta = 0 to 70 C)
Symbol fDAT tSU tHD tCD tOD Parameter Data speed G1, G2, PNCG1 or PCNG2 to DCLKIN Setup G1, G2, PNCG1 or PCNG2 to DCLKIN Hold DCLKIN to ODCLK stable delay ODCLK to any other output stable delay 10 5 20 12 Min. Max. 17 Units Mbps nsecs. nsecs. nsecs. nsecs. Conditions
NODE SYNCHRONIZATION
In a communication system using Viterbi decoding the decoder will only operate correctly when the symbols G1 and G2 are loaded into the decoder in the correct order. Identifying which symbol is which is referred to as node synchronization. The STEL-2030C contains a circuit designed to carry out the node synchronization function automatically. It uses the internally generated metrics of the received sequence to do this. These parameters are constantly changing and are periodically renormalized to keep them within bounds. If renormalization is required too frequently it is a good indication that the system is not converging, and the most likely reason is lack of node synchronization. The renormalization rate at which the system will decide to change the node sync is determined by the threshold parameter. This is an 8-bit number which is set by the THR7-0 inputs. When the renormalization count exceeds this value, the OOS output will go high and the AUTO output will pulse high for one clock cycle. The counter is reset after a number of bits determined by the number set by the COUNT7-0 inputs, so that the threshold must be exceeded somewhere in that period for resynchronization to take place. To use the internal node sync the AUTO output must be connected to the SYNC input. The synchronization sequence depends on the setting of the PARL input. When PARL is set low it is assumed that the data was modulated using BPSK, and when it is set high it is assumed that the data was modulated using QPSK, the appropriate synchronization sequences will be invoked, as shown in the table: Symbol entered into decoder during symbol period N G22-0 G12-0 G1N G2N1 G1N G2N G2N G1N G2N G1N
PARL 0 0 1 1
Sync State 0 1 0 1
Sync state 0 is the state into which the device will be set after a reset sequence. Note that whenever the sync state is changed there will be a delay of 163 or 291 bit periods before valid data starts appearing at DOUT, according to the state of the TBD input. The most suitable threshold setting will depend on both the value of Eb/N0 and the signal level at the G1 and G2 inputs. For full scale inputs, i.e., the peak signal values almost saturate the digital inputs, a suitable starting value for the threshold will be 10%. e.g. if the number of bits over which the measure is made is set to 256 (COUNT7-0 = 0) the threshold should be set to 26 (THR7-0 = 3). More reliable results will be obtained by counting over a longer period to improve the averaging process, but this increases the time taken to make a decision and hence to acquire node sync. Thus starting with a low count period and then increasing it (and adjusting the threshold accordingly to maintain a value of 10%) will result in a faster acquisition of correct node sync followed by a better chance of recorrecting if an error was made.
11
STEL-2030C
PUNCTURED CODE OPERATION
In punctured codes some of the symbols generated by the convolutional encoder are deleted, or punctured, from the transmitted sequence. For example, in an unpunctured Rate 1 /2 sequence, four bits would be transmitted for every two data bits. If every fourth bit was punctured from the sequence then only three bits would be transmitted for every two data bits. This would result in a Rate 2/3 code. The STEL-2030C decoder is designed to operate in punctured mode as well as normal, Rate 1/2, mode. This is easily accomplished by means of the PNCG1 and PNCG2 signals, which delete the symbol which would normally have been loaded into the device at the time when either of these signals is set high. The punctured symbols are replaced by zero metric values. Zero weight is given to these values in the computations relative to the other symbols. The coding gain is significantly less than that for unpunctured operation, as shown in the BER plot, but this is the trade-off for the reduced bandwidth required to transmit the symbols. The puncturing sequences for the various (N-1)/N rates of punctured operation are shown in the table. The sequence shown in boldface is the basic sequence, which is then repeated. The use of the PNCG1 and PNCG2 signals is shown below for Rate 3/4. The sequence is G1 G2 P G2 G1 P. The punctured symbols are marked with asterisks. Rates higher than 3/4 are not recommended with the STEL-2030C.
Rate
2 3
Symbol sequence G1 G2 G1 P G1 G2 G1 P G1 G2 G1 P G1 G2 G1 P G1 G2 G1 G2 P G2 G1 P G1 G2 P G2 G1 P G1 G2 P G2 G1 G2
/3 /4
(a) PARALLEL INPUT MODE (PARL = 1)
G1
* *
* *
*
G2
DCLKIN
PNCG1
PNCG2
(b) SEQUENTIAL INPUT MODE (PARL = 0)
G1/2 G2 G1
*
G2
G1
G2
*
G1
G2
G1
*
G2
G1
G2
*
G1
G2
G1
*
G2
DCLKIN
PNCG1
PNCG2
Note: Timing shown for case where CLKSEL = 1. DCLKIN runs at double the speed when CLKSEL = 0.
STEL-2030C
12
BER PERFORMANCE WITH RATE 1/2 AND PUNCTURED CODES
10 -1
rate=1/2theory rate=1/2 rate=2/3 10 -2 rate=3/4
10
-3
10
-4
BER
-5
10
10
-6
10
-7 1 2 3 4 5 6
Eb/N0 (dB)
APPLICATIONS INFORMATION
BPSK OPERATION OF ENCODER The STEL-2030C encoder generates output symbols as parallel pairs, suitable for QPSK modulation. For BPSK modulation it is normally necessary to serialize the symbol pairs using a clock at twice the data rate. A suitable
STEL-2030C EDAT EG1 EG2 DQ 2X Data Clock Q 74AC74 ( 1/2) ECLKIN
circuit is shown below in which the input clock is divided by two to produce the data clock itself. The encoder produces parallel symbol pairs and the multiplexer serializes them for BPSK modulation.
Data In Data Clock
74AC298 ( 1/4) A2 A1 WS QA BPSK Out
13
STEL-2030C
APPLICATION INFORMATION
The STEL-2030C can be used in a variety of different environments. One example of a system using the convolutional coder and Viterbi decoder is illustrated here. It cannot be used as a common encoder or decoder in multichannel applications because of the memory incorporated on the chip which is dedicated to a single channel. The system modulates a data stream of rate 17 Mbps using binary PSK (BPSK) or quaternary PSK (QPSK). To be able to use convolutional coding/decoding, the system must have available the additional bandwidth needed to transmit symbols at twice the data rate (for rate 1/2 encoding) or make use of two parallel channels (QPSK) to transmit two streams of symbols at the data rate. The performance improvement that can be expected is shown in the graph below. The convolutional encoder is functionally independent from the decoder. A single data bit is clocked into the 7 bit shift register on the rising edge of ECLKIN. The decoder portion of the STEL-2030C is designed to accept symbols synchronously. DCLKIN is supplied by the user to clock in the symbols. The maximum data rate is 17 Mbps, using a clock frequency of 34 MHz. This corresponds to 34 MSymbols per sec at Rate 1/2.
10-1
6 3 2
I Tx DA TA
10-2
6
17 Mbps
RA TE 1/2 CONV . ENCODER
Q
QPSK MODULA TOR CHA NNEL BW= 34 MHz
BER
3 2
10-3
6 3 2
CODED DA TA @ 2 x 17 Mbps I Rx DA TA
Coded
Uncoded
10-4
6
17 Mbps
RA TE 1/2 V ITERBI DECODER
Q
QPSK DEMODULA TOR
3 2
10-5
6 3 2
Coding Gain
CODED DA TA @ 2 x 17 Mbps
10-6
6 3 2
10-7 2
3
4
5
6
7
8 Eb/N 0 dB
9
10
11
12
QPSK Communication System Using Convolutional Encoding and Viterbi Decoding. Rate = 1/2
STEL-2030C
14
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to Intel may make changes to specifications and product descriptions at any time, without notice.
sale and/or use of Intel(R) products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
For Further Information Call or Write
INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888
Copyright (c) Intel Corporation, January 7, 2000. All rights reserved
15
STEL-2030C

▲Up To Search▲

Price & Availability of STEL-2030C

	To Download STEL-2030C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .